Micrel, Inc.
MIC2310
July 2008
15
M9999-070108-A
Secondary OC Detector Trips Circuit Breaker and
Asserts I_FLT
Figure 4 illustrates the behavior of the controller to an
OC event after the primary and secondary OC
detection circuits have been armed (upon the
application of an ENABLE LOW-to-HIGH transition
and after t
POR
) and steady-state operation has been
achieved. Note that the assertion of the controllers
PWRGD digital output occurs when the output load
voltage profile is higher than the controllers V
PGH
threshold voltage and the V
GS
of the external
MOSFET is higher than the controllers V
GSPGH
threshold voltage.
The controllers secondary OC detection threshold is
set by the status of the controllers S[1:0] pins and its
response time is internally set at t
SOCSENSE
as shown in
the ac specification table. When the secondary OC
detector has sensed a very large current surge
(V
CCSENSE
V
SENSE
e V
CBS
), the circuit breaker is
tripped within t
SOCSENSE
. Concurrently, the GATE drive
circuit is disabled and a higher current, fault-mode
pull-down current sink is enabled at the GATE pin.
The DISCH output goes high to (optionally) drive
external pull-down circuitry.
Once the circuit breaker is latched, the I_FLT digital
output is asserted and the PWRGD digital output
becomes de-asserted when the output voltage profile
falls below the controllers V
PGL
threshold voltage or
the V
GS
of the external MOSFET falls below the
controllers V
GSPGH
threshold voltage.
VCC = 12V, nominal
VVREG(UVLOH) = +4.25V
V
REG
= 5V, nominal
Figure 4. Secondary OC Detector Trips Circuit Breaker
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